1. Field of the Invention
The present invention relates to a solid state image sensor, and particularly to a solid state image sensor having a planarized structure under a light shielding metal layer.
2. Description of the Related Art
A solid state image sensor having shift register electrodes formed from a single conductive film has conventionally been manufactured using the following method. FIGS. 1A-C through 4A-C are cross sectional views illustrating the solid state image sensor that has shift register electrodes formed from a single layer of conductive film and is manufactured using a conventional method, in the order of manufacturing steps, in which signs A, B, C correspond to a photoelectric conversion region, a vertical shift register region, a peripheral area, respectively (for example, refer to Japanese Patent No. 2571011). Note that process steps performed before formation of shift register electrodes are not shown in FIGS. 1A-C through 4A-C.
First, an N-type semiconductor substrate 801 is thermally oxidized to form a gate oxide film 802 on the substrate on which a field isolation dielectric 852 is previously and selectively formed. In this case, the field isolation dielectric 852 corresponds to a peripheral area that surrounds an imaging area on which the gate oxide film 802 is formed. That is, the field isolation dielectric 852 is formed so as to surround the gate oxide film 802. It should be noted that this relationship between a set of imaging area and gate oxide film and a set of peripheral area and field isolation dielectric is maintained throughout this specification. Then, a conductive film 803 is deposited over the substrate 801 using low-pressure CVD. Thereafter, separation regions 804 (electrode separation gaps between electrodes) are formed in the conductive film 803 in the imaging area to form shift register electrodes 828 (including vertical and horizontal shift register electrodes) and separation regions 835 are formed in the conductive film 803, in the peripheral area to form shift register electrodes 830 (refer to FIGS. 1A-C).
It should be noted that the width of a gap between the shift register electrodes 828 in the imaging area is determined to be in the range of about 0.25 μm to about 0.5 μm in order to facilitate the transfer of electric charges within a shift register channel (including vertical and horizontal shift register channels). Furthermore, the separation regions 835 are formed between the shift register electrodes 830 in the peripheral area to have a width (e.g., 0.8 μm) longer than the gap between the shift register electrodes 828 in the imaging area in order to prevent a short between the shift register electrodes 830 in the peripheral area, which short is potentially caused around a step portion created by the boundary between the gate oxide film 802 and the field isolation dielectric 852.
Subsequently, a portion, located on a later-formed photoelectric conversion element, of the conductive film 803 that is provided to transfer electric charges and serves also as a readout gate is etched away using a photoresist 833 to form an opening in the conductive film 803 and then dopant ions are implanted through the opening to form a photoelectric conversion element (refer to FIGS. 2A-C).
Thereafter, the photoresist 833 is removed and an interlayer insulation film 806 is formed over the entire structure (refer to FIGS. 3A-C).
Then, a light shielding metal layer 807 is formed on a portion, excluding the photoelectric conversion element, of the interlayer insulation film 806 and metal interconnect lines 808 are formed on the interlayer insulation film 806 in the peripheral area (refer to FIGS. 4A-C).
It should be appreciated that the light shielding metal layer 807 and the metal interconnect lines 808 are simultaneously formed by processing a metal film at the same level.
However, as shown in FIGS. 4B, 4C, the solid state image sensor manufactured using the conventional method is constructed such that particularly, an extremely small spacing is created between the shift register electrodes 830 in the peripheral area after deposition of the interlayer insulation film 806, and therefore, formation of the metal interconnect lines 808 in the peripheral area potentially results in an open circuit 809 due to poor step coverage of the associated metal films over an underlying step, unfavorably causing the image sensor to have deteriorated charge transfer ability. Moreover, when the interlayer insulation film 806 interposed between the metal interconnect lines 808 and diffusion layers, polysilicon electrodes in the peripheral area is thin, parasitic capacitance therebetween becomes large and then causes increase in power consumption of image sensor.
Furthermore, in connection with how such an open circuit condition is prevented from occurring particularly in the metal interconnect lines 808, the idea may occur that the entire surface of the N-type semiconductor substrate 801 is planarized before formation of the metal film 807. However, as shown in FIG. 5, a photoelectric conversion element 919 is also covered with a planarized interlayer insulation film 906 and therefore, a distance “H” between the light shielding metal layer 907 and the surface of the photoelectric conversion element 919 becomes large. Accordingly, light 910 incoming from a direction inclined relative to the normal to the surface of the photoelectric conversion element easily enters a shift register channel 913 underneath a vertical shift register electrode 928, causing the image sensor to have poorer smear characteristics.